1. Field of the Invention
The present invention relates to a transmission signal generating method and related device, and more particularly to a method of generating multilevel transmission signals for a display and related device.
2. Description of the Prior Art
A typical driving system of a liquid crystal display (LCD) includes a timing controller, source drivers and gate drivers. Transmission interfaces commonly used for signal transfer between the timing controller and the source drivers are interfaces with two signal levels, such as reduced swing differential signaling (RSDS) and mini low voltage differential signaling (mini-LVDS) interfaces. For the RSDS interface, the transmission signal, as a two-level signal, has properties of single current intensity and two opposite current directions and can generate a voltage signal having properties of single amplitude and two opposite polarities at the receiving side. With market and technological trends of LCDs, resolution and color performances are advanced, requiring an increase in data and clock rates, realized with a multilevel signal transmission interface using multi-intensity and bidirectional signals. The multilevel signal transmission interface allows more data to be transmitted in one clock cycle.
Bus type signaling or a dedicated type signaling architecture can be used in transmission architecture between the timing controller and the source drivers. The former allows multiple source drivers sharing the same signaling lines coupled to the timing controller, whereas the latter utilizes an independent signaling line pair for each source driver. Please refer to FIGS. 1 and 2, which are respectively schematic diagrams of driving systems 10 and 20 both adopting the dedicated type signaling architecture according to the prior art. In the driving system 10, a timing controller TCON includes a differential signal generator TXi coupled to a source driver CDi via a signaling line pair CDi_P/N including signaling lines CDi_0P, CDi_0N, CDi_1P and CDi_1N, where i is 1-10, and 10 is an amount of source drivers. Outside the source driver CDi, a terminal circuit T is placed between signaling lines CDi_0P and CDi_0N and between signaling lines CDi_1P and CDi_1N as well. The driving system 10 provides a common voltage CDi_VCOM for the terminal circuit T commonly consisting of two cascaded resistors. The timing controller TCON generates multiple-level differential signals sent on the signaling line pair CDi_P/N for the source driver CDi, and thereby the differential signals can generate multiple-level voltage signals with two possible polarities. According to the voltage signals, the source driver CDi can determine types and logic states for the voltage signals for transmission data decoding. As for the driving system 20, the terminal circuit T is installed in the source driver CDi and provided with the common voltage CDi_VCOM. The same operating principle is used in both of the driving systems 10 and 20.
Please refer to FIGS. 3 and 4, which are respectively schematic diagrams of driving systems 30 and 40 according to the prior art. Obviously, the driving systems 30 and 40 have almost the same architecture as the driving systems 10 and 20, respectively. The difference is that the driving systems 30 and 40 both remove the common voltage CDi_VCOM from the terminal circuits T.
In the driving systems 10-40, the transmission signal of the signaling line pair CDi_P/N consists of two signal pairs which each can be transmitted by any two of the signaling lines CDi_0P, CDi_0N, CDi_1P and CDi_1N. For example, the signaling lines CDi_0P and CDi_0N transmit one signal pair, whereas the signaling lines CDi_1P and CDi_1N transmit the other signal pair. Please refer to FIGS. 5 and 6, which are schematic diagrams of waveforms of the transmission signals generated by the timing controller TCON. FIGS. 5 and 6 are respectively signal waveforms under voltage and current modes, and the signaling lines CDi_0P, CDi_0N, CDi_1P and CDi_1N accordingly transmit multilevel voltage and current signals. In FIG. 5, the timing controller TCON generates four current levels of {+3al, +al, −al, −3al} during each transmission, where l is unit current intensity, and ‘a’ is adjustable parameter, and {+} represents a current direction indicating that the timing controller TCON outputs currents via the signaling lines and {−} represents a current direction indicating that the timing controller TCON receives currents from the source drivers. As shown in FIG. 5, the signaling line CDi_1P outputs the 3al current to the source driver CDi during a data symbol period SYM1 and transits to receive the al current to during a data symbol period SYM2, and transits again to output the 3al current during a data symbol period SYM3. From the standpoint of signal matching, during the data symbol period SYM1, the signaling lines CDi_1P and CDi_1N are responsible for the signal pair {+3al, −3al}, whereas the signaling lines CDi_0P and CDi_0N are responsible for the other signal pair {+al, −al}. As can be seen from FIG. 5, the difference of any two neighboring current levels is 2al.
Waveforms in FIG. 6 are the same as those in FIG. 5 and the difference of FIGS. 5 and 6 is that FIG. 6 shows four voltages levels of {+3aV, +aV, −aV, −3aV}, where V is unit voltage, and {+, −} represent two opposite voltage polarities or two voltage polarities according to the common voltage CDi_VCOM. As can be seen from FIG. 6, the difference of any two neighboring voltage levels is 2aV.
In the display, physical channels between the timing controller and the source drivers includes different transmission media, such as package wires, package leads, connectors, flexible printed circuits (FPC), PCB Traces, golden fingers and so forth. Those transmission media could impact the transmission signals and thereby cause channel effects, such as impedance mismatch, coupling and losses. For a large size display, long PCB traces resulting in an increase of the connector number, plus packaging of the timing controller and the source drivers, give rise to stronger channel effects such that the transmission signals are kinked and skewed. Therefore, the source drivers could receive severely distorted signals and thereby degrade the receiving performance.
Please refer to FIGS. 7 and 8. FIG. 7 is a schematic diagram of waveforms of the transmission signal outputted by the timing controller, whereas FIG. 8 is a schematic diagram of waveforms of the transmission signal received by the source driver according to FIG. 7. Transitions of the transmission signals in FIG. 7 are the same as those of the transmission signals in FIG. 5. In FIGS. 7 and 8, the signaling lines CDi_0P, CDi_0N, CDi_1P and CDi_1N are represented by A, D, B and C, respectively. The source driver receives signal pairs of BC and AD according to current thresholds Ith1 and Ith2. Tt1, Tr1, Tt4 and Tr4 are time points where current difference of the AD signal pair becomes greater than the current threshold Ith2 after a waveform crossing appears in the AD signal pair. Tt2, Tr2, Tt3 and Tr3 are time points where current difference of the BC signal pair becomes greater than the current threshold Ith1 after a waveform crossing appears in the BC signal pair. Valid data durations width_t1 and width_r1 are equal to (Tt3-Tt2) and (Tr3-Tr2), respectively. Skew amounts Skew_t1, Skew_t2, Skew_r1 and Skew_r2 are equal to (Tt2-Tt1), (Tt4-Tt3), (Tr2-Tr1) and (Tr4-Tr3), respectively. From comparison of FIGS. 7 and 8, the skew amounts Skew_r1 and Skew_r1 are respectively greater than the skew amounts Skew_t1 and Skew_t2, and the valid data durations width_t1 is shorter than width_r1. Thus, the kink effect results in greater skew amounts and shorter valid data durations after the transmission signal passes through the transmission channels.
Please refer to FIG. 9, which is a schematic diagram of waveforms of another transmission signals received by the source driver. Transitions of the transmission signals in FIG. 9 are different from those of the transmission signals in FIG. 7. Considering the signal line B, current transitions during the data symbol periods SYM4 to SYM6 are {+3al}, {+3al} and {+al}. The source driver receives the signal pair AD according to the current threshold Ith2 and receives the signal pair BC according to the current thresholds Ith3 and Ith4. Current difference of the signal pair AD becomes greater than current threshold Ith2 at a time point Tr5 after a waveform crossing appears in the signal pair AD; Tr6 is a time point where current differences of the signal pairs BA and DC respectively become greater than current threshold Ith3 and Ith4 after a waveform crossing appears in the signal pairs BA and DC; Tr7 is a time point where current differences of the signal pairs BA and DC respectively become greater than current threshold Ith3 and Ith4 after a waveform crossing appears once more in the signal pairs BA and DC. A valid data duration width_r3 is equal to (Tr7-Tr6), and a skew amount Skew_r5 is equal to (Tr6-Tr5). As can be seen from the transmission signal in FIG. 9, the channel effect causes kinks resulting in extension of the skew amount.
Therefore, in the prior art, the valid durations for data reception are shortened due to channel effects, thereby resulting in a higher bit error rate.